1. Field of the Invention
The present invention relates to an analog to digital converter circuit (referred to as an AD converter circuit hereinafter) that converts an analog signal into a digital signal. In particular, the present invention relates to an AD converter circuit of successive approximation type.
2. Description of the Prior Art
In recent microstructure CMOS processes, a power supply voltage (Vdd) has been lowered according to a scaling rule of devices. In order to reduce a consumption power in a standby state of a large-scale digital circuit, however, a threshold voltage Vth of each of P channel MOSFETs and N channel MOSFETs that constitutes a CMOS device has not been reduced yet according to the scaling rule and a Vth/Vdd that is a ratio of the threshold voltage Vth to the power supply voltage Vdd is increasing. A CMOS device manufactured using, for example, 0.35 micrometer technique has a power supply voltage Vdd of 3.3 V and a threshold voltage Vth of 0.7 V. A CMOS device manufactured using, for example, 0.18 micrometer technique has a power supply voltage Vdd of 1.5 V and a threshold voltage Vth of about 0.5 V.
As for a logic LSI having CMOS devices integrated at high density, it is effective to reduce the power supply voltage Vdd so as to reduce the consumption power. However, as the Vth/Vdd ratio increases, an ordinary CMOS analog switch as configured by a P channel MOSFET and an N channel MOSFET cannot be used.
FIG. 21 is a circuit diagram showing a configuration of a conventional CMOS analog switch circuit. FIG. 22 is a graph showing an operation of the CMOS analog switch shown in FIG. 21, and shows conductances Gp and Gn of a MOSFET P101 and a MOSFET N101 relative to an input voltage Vin.
Referring to FIG. 21, a circuit, in which two MOSFETs P101 and N101 are connected in series, is inserted between an input terminal T101 and an output terminal T102, and a load capacitance Cload is connected to an output terminal T102. As shown in FIG. 22, when the input voltage Vin increases from 0 V, the conductance Gp of the P channel MOSFET P101 rises from 0 at a threshold voltage Vthp (it is noted that that a threshold voltage between the power supply voltage Vdd and the threshold voltage Vthp is referred to as a Vthpa) and the state of the MOSFET P101 is changed from an ON state to an OFF state. When the input voltage Vin is lowered from the power supply voltage Vdd, the conductance Gn of the N channel MOSFET N101 rises from 0 at a threshold voltage Vthn (it is noted that a threshold voltage between a grounding voltage Vss and the threshold voltage Vthn is referred to as a Vthna) and the state of the MOSFET N101 is changed from an ON state to an OFF state.
When the power supply voltage Vdd is lowered to, for example, 1V, the conductances Gp and Gn of the P channel MOSFET P101 and the N channel MOSFET N101 that constitute the CMOS analog switch shown in FIG. 21 decreases at the input voltage Vin near Vdd/2 even if the P channel MOSFET P101 and the N channel MOSFET N101 are turned on, and this leads to that the CMOS analog switch is not turned on. In such conditions, there is caused such a problem that it is difficult to realize an AD converter circuit or a digital to analog converter (referred to as a DA converter hereinafter) using an analog switch.
In order to solve the above-mentioned problem, when the threshold voltage Vth of the MOSFET is lowered, the ON resistance thereof decreases but an OFF resistance is not sufficiently high so that a leak current increases. This leads to that the analog switch cannot be used. As another method for solving this problem, there has been known to those skilled in the art, a method for raising a gate voltage of each MOSFET that constitutes the analog switch to be higher than the power supply voltage Vdd. In order to implement this method, there has been provided a method for obtaining a high gate voltage using a charge pump, and further, there has been provided a bootstrapping method for obtaining a high gate voltage by holding electric charges charged into a capacitor and connecting the capacitor to a power supply in series. However, these methods requires a device having a withstand voltage higher than that of an ordinary device, and this leads to such problems as complication of the process, deterioration of the reliability, and increase in the circuit area.
FIG. 23 is a circuit diagram showing a configuration of an AD converter circuit according to a first prior art example. FIG. 24 is a circuit diagram showing a configuration of a DA converter 16 of capacitor array type shown in FIG. 23. The AD converter circuit shown in FIG. 23 is configured to include the DA converter 16 of capacitor array type, a comparator 13, a successive approximation register (SAR) 14, and a control logic circuit 15. In the DA converter 16 of capacitor array type shown in FIG. 23, respective capacitors 160-0 to 160-N of the capacitor array also function as capacitors for sampling and holding. Furthermore, the DA converter 16 of capacitor array type is configured to include the capacitors 160-0 to 160-N and CMOS analog switches 161-0 to 161-N respectively connected to the respective capacitors 160-0 to 160-N. Thus, numerous LSIs have been developed using the CMOS techniques.
In the DA converter 16 of capacitor array type shown in FIG. 24, the switches 161-0 to 161-N connected to a reference voltage Vrefp having a higher potential (e.g., the power supply voltage source Vdd) or a reference voltage having a lower potential (e.g., the grounding voltage Vss) can be realized by P channel MOSFETs or N channel MOSFETs, respectively. In addition, each switch is configured as a grounded switch having one end grounded or being connected to the higher-potential power supply voltage source, so that the switch can be turned on and off even at a low power supply voltage. However, the potentials at both ends of each of a switch 162 and the switches 161-0 to 161-N are in a floating state, and this leads to that at the lower power supply voltage shown in FIG. 21, the ON resistance of each switch is quite high and the switch does not operate normally.
In order to solve above-mentioned problems, in a non-patent document of Jens Sauerbrey et al., “A 0.5V, 1 mW Successive Approximation ADC”, Proceedings of 28th European Solid-State Circuit Conference (ESSCIRC 2002), September 2002, Firenze, Italy, pp. 247–250, there is proposed an AD converter circuit of successive approximation type that operates at a low voltage like about 1V using a DA converter based on a grounded switch (referred to as a second prior art example hereinafter). FIG. 25 is a circuit diagram showing a configuration of the AD converter circuit according to the second prior art example, and FIG. 26 is a circuit diagram showing a configuration of a DA converter 19 of capacitor array type shown in FIG. 25. As shown in FIG. 25, the AD converter circuit according to the second prior art example is configured to include the following components:
(a) A sample hold circuit 18 that samples an input analog signal inputted via an analog signal input terminal 90a, and that holds a sample value until end of AD conversion.
(b) A DA converter 19 of capacitor type.
(c) A comparator 13 that compares an output voltage 18a from the sample hold circuit 18 with an output voltage 19a from the DA converter 19, and that outputs a comparison result signal.
(d) A successive approximation register (SAR) 14 that controls the DA converter 19 based on the comparison result signal from the comparator 13.
(e) A control logic circuit 15 that controls operation timings of the respective circuits 13, 14, 18 and 19.
As shown in FIG. 25, the DA converter 19 is configured to include the following components:
(a) Capacitors 190-0 to 190-N having capacitances Co to CN, respectively.
(b) Switches 191-1 to 191-N for selectively connecting the respective capacitors 190-0 to 190-N to either a reference voltage source Vrefp having a higher potential or a reference voltage source Vrefn having a lower potential.
(c) A switch 192-0 for grounding the output voltage 19a from the DA converter 19 via a capacitor 192-1.
(d) The capacitor 192-1 having a capacitance Cs for attenuating or damping the maximum value of the output voltage 19a from the DA converter 19 to Vdd/2.
Assuming that C0=Cunit is a unit capacitance, respective capacitances Ci (i=1, 2, . . . N) are set as represented by the following Equations (1) to (3):C1=C0=Cunit  (1),Ci+1=2Ci (i=1, 2, . . . , N−1)  (2),andCS=2CN  (3).
Each of the switches 191-1 to 191-N of the DA converter 19 is a grounded switch connected to the reference voltage source Vrefp having the higher potential or the reference voltage source Vrefn having the lower potential. Therefore, the switch having the higher potential can be realized by a P channel MOSFET, and the switch having the lower potential can be realized by an N channel MOSFET. Each of the switches can be turned on and off even at a lower power supply voltage.
Further, the maximum output voltage V19amax from the DA converter 19 is obtained when the switches 191-1 to 191-N are connected to the higher-potential reference voltage source Vrefp, and then, it is represented by the following Equation (4):                                                                         V                                  19                  ⁢                                                                          ⁢                  max                                            =                            ⁢                              Vrefp                ×                                                      (                                                                  C                        N                                            +                                              C                                                  N                          -                          1                                                                    +                      …                      ⁢                                                                                          +                                              C                        1                                            +                                              C                        0                                                              )                                    /                                                                                                                      ⁢                                                C                  S                                +                                  C                  N                                +                                  C                                      N                    -                    1                                                  +                …                ⁢                                                                  +                                  C                  1                                +                                  C                  0                                            )                                                                          =                            ⁢                              Vrefp                /                2                                                                        (        4        )            
Therefore, the input signal of the AD converter circuit is ranged from a voltage Vrefn to a voltage Vrefp/2. In order to enlarge the input voltage range, a voltage of the higher-potential power supply voltage source Vrefp is set to be equal to that of the power supply voltage source Vdd, and a voltage of the lower-potential power supply voltage source Vrefn is set to be equal to a ground potential (0 V). In this case, the input signal range is ranged from 0 V to the voltage Vdd/2.
The AD converter circuit of capacitor array successive approximation type using the ordinary analog switches according to the first prior art example can not operate at a voltage equal to or lower than 1 V since the switches are not turned on at 1V or lower. The AD converter circuit according to the second prior art example that is an improvement of the AD converter circuit according to the first prior art example can operate at a power supply voltage of 1 V. However, the input voltage range is limited to a range from the ground potential to the voltage Vdd/2. In addition, the comparator 13 should operate at a high rate at the input voltage in a relatively wide common mode voltage range from 0 V to the voltage Vdd/2. It is difficult to realize the differential comparator 13 that operates at such a wide common mode voltage by an ordinary circuit configuration.
The comparator 13 shown in FIG. 25 sets the output voltage 18a from the sample hold circuit 18 as a reference voltage, and compares the reference voltage with the output voltage 19a from the DA converter 19a. In order to set the voltage range of the analog input signal of the AD converter circuit from the ground potential to the voltage Vdd of the power supply voltage source, it is necessary for the comparator 13 to compare a minor potential difference in a wide voltage range from a voltage near the ground potential to the voltage Vdd. It is difficult to realize this by the comparator 13 with the ordinary circuit configuration. Furthermore, when the comparator 13 is configured using a rail to rail amplifier circuit (having a full range from a lower limit voltage to a higher limit voltage of the power supply), there is a possibility that the input voltage range may be able to be enlarged. However, this leads to such problems as complication of the circuit configuration, decrease in the operation rate, and increase in the power consumption.